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| PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) FEATURES * * * * * * * * Spread Spectrum Clock Generator/Multiplier with output selectable from 1x to 8x. 13MHz to 240MHz output with output enable. 13MHz to 30 MHz reference input frequency accepted from crystal or external clock signal. Reduced EMI from Spread Spectrum Modulation, with selectable modulation amplitude for Center Spread, Down Spread or Asymmetric Spread. TTL/CMOS compatible outputs. 3.3V Operating Voltage. 150 ps maximum cycle-to-cycle jitter. Available in 16-Pin 150mil SSOP or DIE. PACKAGE PIN CONFIGURATION XIN/FIN XOUT/SD0*^ M2^ M1^ M0^ SC0^ SC1^ SC2^ 1 2 16 15 GND AVDD REF/SD1*^ VDD SC3^ OE^ FOUT GND PLL 701-10 3 4 5 6 7 8 14 13 12 11 10 9 XIN/FIN = 10 ~ 30 MHz DESCRIPTION The PLL701-10 is a low EMI Clock Generator and Multiplier for high-speed digital systems. It uses Spread Spectrum Technology (SST) and permits different levels of EMI reduction by selecting the amplitude of the applied SST. The SST feature can be turned off. An output enable input is also used. The chip operates with input frequencies ranging from 13 to 30 MHz and provides 1x to 8x at its output. DIE PAD CONFIGURATION 69 mil AVDD GND GND XIN 1700, 2540 18 AVDD XOUT/SD0*^ 23 22 21 (Optional) 20 (Optional) 19 GNDOSC 25 C501A A0404 -04A 17 16 15 14 13 12 AVDD REF/SD1*^ VDD VDD (optional) VDD (optional) SC3^ OUTPUT CLOCK (FOUT) SELECTION M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 FIN/XIN (MHz) 13 ~ 28 13 ~ 28 14 ~ 30 13 ~ 28 20 ~ 30 17 ~ 30 15 ~ 30 13 ~ 28 Multiplier X1 X2 X3 X4 X5 X6 X7 X8 FOUT (MHz) 13 ~ 28 26 ~ 56 42 ~ 90 52 ~ 112 100 ~ 150 102 ~ 180 105 ~ 210 104 ~ 224 104 mil M2^ M1^ M0^ 28 29 30 10 OE^ SC0^ SC1^ 34 35 1 45 6 8 7 FOUT GNDBUF SC2^ GND GND GND Y X BLOCK DIAGRAM XIN XOUT M(0:2) SD(0:1) SC(0:3) OE XTAL OSC PLL SST Control Logic FOUT Note: ^: Internal pull-up resistor (120k for SD0, 30 k for SC0SC2, SD1, M0-M2 and OE). The internal pull-up resistor results in a default high value when no pull-down resistor is connected to this pin. *: SD0 and SD1 are latched upon power-up. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) SPREAD SPECTRUM SELECTION TABLE SD1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SD0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SC3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SC2 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SC1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SC0 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Modulation Modulation Magnitude Frequency 0.250% 0.500% 0.750% 1.000% 1.250% 1.500% 1.750% 2.000% C C C C D C A C A C A C A D C A A C A A C A A C D A A C A A A C A A A C A A A Modulation Type 0.125% 0.25% 0.375% 0.50% -1.00% 0.625% +0.125 ~ -1.125% 0.75% +0.25 ~ -1.25% 0.875% +0.375 ~ -1.375% 1.00% +0.50 ~ -1.5% -2.00% 1.125% +0.625 ~ -1.625% +0.125 ~ -2.125% 1.25% +0.25 ~ -2.25% +0.75 ~ -1.75% 1.375% +0.875 ~ -1.875% +0.375 ~ -2.375% 1.50% -3.00% +1.00 ~ -2.00% +0.50 ~ -2.50% 1.625% +1.125 ~ -2.125% +0.625 ~ -2.625% +0.125 ~ -3.125% 1.75% +1.25 ~ -2.25% +0.75 ~ -2.75% +0.25 ~ -3.25% 1.875% +1.37 ~ -2.375% +0.875 ~ -2.875% +0.375 ~ -3.375% SST turned off SST turned off SST turned off SST turned off 2.250% 2.500% 2.750% Fin / 512 3.000% 3.250% 3.500% 3.750% 0.00 % Notes: C: Center Spread. A: Asymmetric Spread. D: Down Spread. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) PIN/PAD DESCRIPTIONS Name XIN/FIN XOUT/SD0 M2 M1 M0 SC0 SC1 SC2 SC3 FOUT OE VDD REF/SD1 AVDD GNDOSC GNDBUF GND Pin # 1 2 3 4 5 6 7 8 12 10 11 13 14 15 N/A N/A 9 and 16 Pad # 22 23 28 29 30 34 35 1 12 8 10 13,14,15 16 17,18,19 25 7 4,5,6,20,21 Type I B I I I I I I I O I P B P P P P Description Crystal input to be connected to fundamental parallel mode crystal. (CL=20pF) or clock input. At power-up, this pin is acts as input pin to select the modulation rate and is latched in. After the input sampling, it is used as crystal output connector. 120k internal pull up resistor. Digital control input to select output frequency. 30k internal pullup. Digital control input to select output frequency. 30k internal pullup. Digital control input to select output frequency. 30k internal pullup. Digital control input to select spread spectrum modulation. 30k internal pull-up. Digital control input to select spread spectrum modulation. 30k internal pull-up. Digital control input to select spread spectrum modulation. 30k internal pull-up. Digital control input to select spread spectrum modulation. 30k internal pull-up. Modulated Clock Frequency Output. The frequency before modulation is synthesized by multiplying the input frequency by 1X to 8X, depending on SD(0:1) and SC(0:3). Output Enable. When low, Tri-states all outputs. 30k internal pull-up. 3.3V Power Supply. At power-up, this pin acts as input pin to select the modulation rate and is latched in. After the input sampling, this pin provides a buffered Reference Clock Output of the same frequency as the crystal or clock input. 30k internal pull-up. 3.3V Analog power supply. Ground for Oscillator circuitry. Ground for output buffer circuitry. Ground. Notes: B - bi-directional pin; I - input pin; P - power supply/ground pin. DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 104 x 69 mil GND 80 micron x 80 micron 10 mil 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) FUNCTIONAL DESCRIPTION Selectable spread spectrum and modulation rates The PLL701-10 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation, as well as selectable modulation rate. Selection is made by connecting specific input pins to a logical "zero" or "one". Pins 6 (SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation as shown on the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as inputs to select the output frequency as shown on the output clock selection table (page 1). Pin 11 is the output enable pin, that tri-states all outputs when low (logical "zero"). In order to reduce the number of pins on the chip, the PLL701-10 uses pin 2 and 14 (XOUT/SD0 and REF/SD1) as a bi-directional pin. The pins serve as modulation rate selector inputs (SD0 and SD1) upon power-up (see modulation rate table on page 1), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon as the inputs have been latched. Connecting a selection pin to a logical "one" All selection pins have an internal pull-up resistor (30k for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120k for pin 2). This internal pull-up resistor will pull the input value to a logical "one" (pull-up) by default, i.e. when no resistive load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a logical "one" upon power-up. Connecting a selection pin to a logical "zero" For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be grounded to pull the input down to a logical "zero". Connecting the bi-directional pins (SD0 and SD1) to a logical "zero" will however require the use of an external loading resistor between the pin and GND that has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around Rup/4 (e.g. 27k for pin 2 and 4.7k for pin 14, see Application Diagram). APPLICATION DIAGRAM FOR OUTPUT AND MODULATION SELECTION Internal to chip VDD External Circuitry Rup Power Up Reset R RB XIN EN Bi-directional pin Clock Load SD0 or SC0~SC2 Latch Rup/4 Jumper options NOTE: Rup=120k for SD0 (Pin2); and Rup=30k for SD1(Pin 14). R starts from 1 to 0 while RB starts from 0 to 1. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. DC/AC Specifications PARAMETERS Supply Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Input Frequency Maximum interruption of FIN Load Capacitance Pull-up Resistor Pull-up Resistor Short Circuit Current 3.3V Dynamic Supply Current CL Rup Rup Isc ICC SYMBOL VDD VIH VIL IIH IIL VOH VOL FXIN FIN CONDITIONS MIN. 2.97 0.7* VDD TYP. MAX. 3.63 0.3* VDD 100 100 UNITS V V V A A IOH=5mA, VDD =3.3V IOL=6mA, VDD =3.3V When using a crystal When using reference clock When using reference clock Between Pin XIN and XOUT* PIN 2 PIN 3,4,5,6,7,8,11,12 No Load 2.4 15 15 18 120 30 25 20 0.4 30 30 100 MHz MHz s pF k k mA mA *Note: Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN with a reference clock signal, the load capacitance will be 36pF (typical). 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) 3. TIMING CHARACTERISTICS PARAMETERS Rise Time Fall Time Output Duty Cycle Cycle to Cycle Jitter Cycle to Cycle Jitter SYMBOL Tr Tf DT Tcyc-cyc Tcyc-cyc CONDITIONS Measured at 0.8V ~ 2.0V @ 3.3V Measured at 2.0V ~ 0.8V @ 3.3V X1, X2, X4, X8 FOUT @ 3.3V X3, X5, X6, X7 FOUT @ 3.3V MIN. 0.8 0.78 45 TYP. 0.95 0.85 50 MAX. 1.1 0.9 55 100 150 UNITS ns ns % ps ps 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) PAD ASSIGNMENT Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 (LOWER LEFT CORNER: X = 0, Y = 0) Name SC2 N/C N/C GND GND GND GNDBUF FOUT N/C OE N/C SC3 VDD (Optional) VDD (Optional) VDD REF/SD1 AVDD AVDD AVDD GND (Optional) GND (Optional) XIN XOUT/SD0 N/C GNDOSC N/C N/C M2 M1 N/C N/C N/C N/C SC0 SC1 X (m) 338.9 569 780.5 1027.6 1127.3 1284.5 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1595.1 1369.2 1037.3 824.7 529.7 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 105.6 Y (m) 104.7 104.7 104.7 104.7 104.7 104.7 139.7 381.7 596.3 811.9 970.3 1069.3 1312.3 1555.6 1656.8 1879.9 2093 2390.6 2435 2435 2435 2435 2343.5 2136.1 2035.6 1934.9 1741.5 1641.4 1396.2 1180.3 993.5 836.7 680.1 354.9 110.7 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7 PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) PACKAGE INFORMATION 16 PIN SSOP mm Symbol A A1 B C D E H L e Min. 1.35 0.10 0.20 0.18 4.80 3.81 5.79 0.41 Max. 1.75 0.25 0.30 0.25 5.00 3.99 6.20 1.27 Min. 0.053 0.004 0.008 0.007 0.189 0.150 0.228 0.016 BSC Max. 0.069 0.010 0.012 0.010 0.197 0.157 0.244 0.050 A1 B D E H A C L e 0.635 BASIC 0.025 BASIC ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL701-10 X C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE X=SSOP; D=DIE Order Number PLL701-10XC PLL701-10XC-R PLL701-10DC Marking P701-10XC P701-10XC P701-10DC Package Option SSOP -Tubes SSOP -Tape & Reel Die -Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8 |
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